1. Technical Field
The present invention relates to integrated circuits and more particularly to a programmable pulsewidth circuit and delay circuit that permits adjustment to signals in accordance with different operations on a chip.
2. Description of the Related Art
Microprocessor yields can be determined by array yield parameters such as minimum voltage (Vmin), cell stability, and array performance. Different techniques have been proposed to improve the stability of static random access memory (SRAM) cells such as dynamic or dual cell power supplies based on read or write operations, usage of multi-threshold voltage (Vt) devices, or adding transistors to a six transistor (6T) SRAM cell.
An extension of this is the usage of an eight transistor (8T) cell where read and write ports are decoupled. However, the write port of an 8T SRAM suffers the same half select problems as that of 6T cells.
In addition, with the additional device densities of new designs, it has become increasingly difficult to test integrated circuits. It has become preferable to employ built-in self testing features on chips to permit individual testing of components, to provide the ability to learn as much information as possible in case of a failure and to test proper function of components.
To this end, independent clock blocks for critical paths in a chip design and for testing are currently unavailable on-chip. Fine control of clock pulsewidth and delays is a major issue for powering and depowering VLSI control circuits. In addition, debugging of individual paths (e.g., read/write, data, reset, etc.) in VLSI circuits is also an important problem that needs to be addressed.